Integrated circuit structure formed by damascene process

ABSTRACT

An integrated circuit structure is formed using a damascene process that involves forming a trench or cavity for the structure in a temporary layer of material. A conductive material, such as copper, can then be deposited on the temporary layer to overfill the trench or cavity, and the excess conductive material can be removed by polishing down to the surface of the temporary layer. The integrated circuit structure can then be exposed by removing the temporary layer. One example of an integrated circuit structure that can be formed using this method is an upper electrode in an MRAM array. By using the process to form an upper electrode in an MRAM array, the process of forming a magnetic keeper around the upper electrode is advantageously simplified.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of U.S. application Ser.No. 10/655,666, filed Sep. 5, 2003, the entirety of which isincorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to integrated circuit structures. Morespecifically, the present invention relates to integrated circuitstructures formed by damascene processes.

2. Description of the Related Art

Integrated circuit structures comprising certain metals, such asaluminum, can be formed by depositing a layer of the metal on asubstrate, patterning the metal with photoresist, and selectively dryetching the metal to form the desired structure. Other metals, such ascopper, can be difficult to dry etch. Nevertheless, integrated circuitstructures can be formed from such metals by using a damascene process.In a damascene process, a layer of insulating material is deposited on asubstrate, patterned with photoresist, and selectively etched to formtrenches or cavities for the desired metallic structures. The metal canthen be deposited on the insulating layer to overfill the trenches orcavities, and the excess metal can be removed by polishing down to thesurface of the insulating layer.

One example of an integrated circuit structure commonly formed using adamascene process is a conductive line in a magnetic random accessmemory (MRAM) device. An MRAM device typically comprises a plurality ofmagnetic memory cells organized into an array having any of a widevariety of configurations. One exemplary configuration is a“cross-point” memory array, which comprises a first set of parallelconductive lines covered by an insulating layer, over which lies asecond set of parallel conductive lines, perpendicular to the firstlines. One set of conductive lines is referred to as the “bit” lines,and the other set of conductive lines is referred to as the “word”lines. The magnetic memory cells can be sandwiched between the bit linesand the word lines at their intersections. Due to the high currentdemands of an MRAM device, the bit lines and word lines of the array areoften made of copper.

When current flows through a bit line or a word line, it generates amagnetic field around the line. In a typical MRAM device, the state of agiven memory cell can be switched by flowing current through the wordline and the bit line corresponding to the memory cell. The sum of thetwo generated fields is sufficient to switch or “flip” the bit.

However, as the density of magnetic memory cells within an arrayincreases, so does the possibility of cross talk between a bit line or aword line and nearby memory cells, which can cause unintended switchingof memory cells. To reduce the likelihood of such cross talk, it isdesirable to localize the magnetic field generated by a word line or abit line carrying current. One approach for localizing this magneticfield is to surround each word line and bit line within an MRAM arraywith a magnetic keeper. For example, U.S. Pat. No. 6,413,788, which ishereby incorporated by reference in its entirety, discloses a variety ofmagnetic keeper configurations and methods of forming such magnetickeepers.

SUMMARY OF THE INVENTION

In one embodiment of the present invention, a magnetic memory device inan integrated circuit comprises a lower electrode formed over asemiconductor substrate and a magnetic memory cell formed over the lowerelectrode. The magnetic memory device further comprises an upperelectrode with a bottom surface facing toward the magnetic memory cell,a top surface facing away from the magnetic memory cell and two sidesurfaces facing away from the magnetic memory cell. The magnetic memorydevice further comprises a magnetic keeper comprising at least onecontinuous layer of magnetic material covering the top surface and atleast two side surfaces of the upper electrode.

In another embodiment, an integrated circuit element comprises a copperstructure having a top surface and at least two side surfaces and acoating comprising a continuous layer of material adjacent to the topsurface and at least two side surfaces of the copper structure.

In another embodiment, a method of forming an electrode in an MRAMdevice comprises forming a conductive line in a trench within atemporary layer using a damascene process, the conductive line having abottom surface facing toward a magnetic memory cell, a top surfacefacing away from the magnetic memory cell, and two side surfaces facingaway from the magnetic memory cell. The method further comprisesremoving the temporary layer such that the top surface and at least twoside surfaces of the conductive line are exposed.

In another embodiment, a method of forming an integrated circuitstructure comprises providing a temporary layer having an upper surface,etching a cavity into the temporary layer, and filling the cavity withcopper such that a copper structure is formed within the cavity. Themethod further comprises planarizing the copper with the upper surfaceof the temporary layer and selectively etching the temporary layer suchthat the copper structure is exposed.

In another embodiment, a method of forming an integrated circuit elementcomprises providing a temporary layer having an upper surface, etching acavity into the temporary layer, and depositing a layer of a firstconductive material over the temporary layer, thereby forming aconductive structure within the cavity. The method further comprisesplanarizing the layer of first conductive material with the uppersurface of the temporary layer, selectively etching the temporary layer,thereby exposing an upper surface and at least two side surfaces of theconductive structure, and covering the upper surface and at least twoside surfaces of the conductive structure with a continuous layer of asecond conductive material.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features and advantages of the invention will now bedescribed with reference to the drawings of certain preferredembodiments, which are intended to illustrate, and not to limit, theinvention.

FIG. 1 illustrates a cross-sectional view of a partially fabricated MRAMstructure.

FIG. 2 illustrates the partially fabricated MRAM structure of FIG. 1after a damascene trench has been formed in a temporary layer abovemagnetic bits.

FIG. 3 illustrates the partially fabricated MRAM structure of FIG. 2after the damascene trench has been lined with a barrier material,filled with metal, and planarized.

FIG. 4 illustrates the partially fabricated MRAM structure of FIG. 3after the conductive line has been exposed by removing the temporarylayer.

FIG. 5 illustrates the partially fabricated MRAM structure of FIG. 4after the conductive line has been surrounded by a magnetic keeper.

FIG. 6 illustrates the partially fabricated MRAM structure of FIG. 5after an insulating layer has been formed over the conductive line.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention relates to integrated circuit structures formed bya damascene process. The structures typically comprise a conductivematerial that is difficult to dry etch, such as, for example, copper. Inthe following description of exemplary embodiments of the invention, thestructures are described as comprising copper. Those of ordinary skillin the art will understand, however, that the structures may comprise avariety of other suitable materials.

In some embodiments, the damascene process begins by forming a temporarylayer of material on a substrate. It should be understood that theinitial layer is referred to as a “temporary” layer because it iseventually removed during the damascene process, and not because itnecessarily constitutes a material that is typically associated withtemporary structures in the art of integrated circuit fabrication.Indeed, the temporary layer may comprise any material that isselectively etchable relative to copper and other materials adjacent tothe temporary layer. Therefore, while the temporary layer in someembodiments may comprise a material that is typically associated withtemporary structures in the art of integrated circuit fabrication, thetemporary layer in other embodiments may comprise any of a wide varietyof materials that are typically associated with more permanentstructures.

Following the formation of the temporary layer, trenches or cavities forthe desired structures can be formed in the temporary layer. Copper canthen be deposited on the temporary layer to overfill the trenches orcavities, and the excess copper can be removed by polishing down to thesurface of the temporary layer. The copper structures can then beexposed by removing the temporary layer.

Unlike the damascene process described above, conventional damasceneprocesses do not begin by depositing a temporary layer that is laterremoved. Instead, the initial layer deposited in a conventionaldamascene process typically remains in place when the process iscomplete. Thus, unlike the damascene process described above, aconventional damascene process results in a structure that is imbeddedin a layer of material rather than an exposed structure.

The damascene process described above can be used to form a wide varietyof integrated circuit structures. For example, in some embodiments, theprocess is used to form a plurality of copper conductive lines in anMRAM array. Examples of these embodiments are described in more detailbelow. For purposes of illustration, these embodiments will be describedin the context of an MRAM device having a particular configuration. Thedetails associated with this specific configuration are set forth toillustrate, and not to limit, the invention. The scope of the inventionis defined only by the appended claims.

FIG. 1 illustrates a cross-sectional view of a partially fabricated MRAMstructure. In the illustrated embodiment, the structure includes amagnetic memory cell 24 formed over a lower electrode 10 comprising alower conductive line 12 surrounded by a barrier layer 14. In someembodiments, the lower conductive line 12 comprises copper, and thebarrier layer 14 comprises tantalum, tantalum nitride, or anothermaterial that blocks the diffusion of copper and is compatible withintegrated circuit manufacture.

The lower electrode 10 runs from side to side across the page and, inthe cross-sectional view of FIG. 1, is cut near the center along itslong axis. As a result, only the portions of the barrier layer 14 thatclad the lower conductive line 12 along the upper surface 18 and thelower surface 20 can be seen. The cladding along one side of the lowerconductive line 12 is above the plane of the page and along the otherside of the lower conductive line 12 is below the plane of the page. Insome embodiments, there is no barrier layer 14 along the upper surface18 of the lower conductive line 12. In these embodiments, the magneticmemory cell 24 is formed directly on top of the lower conductive line12.

In some embodiments, the lower conductive line 12, aside from the uppersurface 18, is surrounded by a magnetic keeper. A magnetic keeper maycomprise any structure that tends to localize the magnetic fieldgenerated by a conductive line carrying a current. For example, in someembodiments, the magnetic keeper comprises a layer of soft magneticmaterial sandwiched between two barrier layers. It should be understood,however, that the barrier layers are typically not necessary to confinethe magnetic field generated by a conductive line carrying a current.Thus, in other embodiments, the magnetic keeper comprises only a singlelayer of magnetic material. The top surface 18 of the lower conductiveline 12 preferably has no magnetic keeper because it may interfere withthe interaction between the lower electrode 10 and the magnetic memorycell 24. U.S. Pat. No. 5,956,267, which is hereby incorporated byreference in its entirety, discloses a variety of magnetic keeperconfigurations for lower electrodes and methods of forming such magnetickeepers.

The magnetic memory cell 24 may comprise any magnetic structure thatstores digital bits of data, including thin ferromagnetic films or morecomplex layered magnetic thin-film structures, such as tunnelingmagnetoresistance (TMR) or giant magnetoresistance (GMR) elements. Forexample, in the illustrated embodiment, the magnetic memory cell 24comprises a conventional TMR structure, which comprises a firstferromagnetic layer 30, a barrier layer 32, and a second ferromagneticlayer 34. The magnetic memory cell 24 may be formed using a variety ofmethods and materials that are well-known to those of skill in the art.

For example, in some embodiments, the first ferromagnetic layer 30 maycomprise a stack of magnetic and associated adjacent sublayers, such as,for example, a tantalum seed sublayer, a nickel-iron seed sublayer, aniridium manganese pinning sublayer and a nickel-iron ornickel-iron-cobalt sublayer. The barrier layer 32 may comprise, forexample, aluminum oxide, having a thickness within the range of about0.5 nm to about 3 nm, preferably within the range of about 1 nm to about2 nm. Like the first ferromagnetic layer 30, the second ferromagneticlayer 34 may comprise a stack of magnetic and associated adjacentblanket sublayers, such as, for example, a nickel-iron ornickel-iron-cobalt sublayer, a tantalum barrier sublayer and a tungstennitride sublayer. The first ferromagnetic layer 30 and the secondferromagnetic layer 34 may each have a thickness within the range ofabout 10 nm to about 60 nm, more preferably within the range of about 20nm to about 50 nm.

In the illustrated embodiment, the magnetic memory cell 24 is surroundedby an insulating layer 26, which can also be formed using a variety ofwell-known methods and materials. For example, in some embodiments, theinsulating layer 26 comprises silicon nitride or a form of siliconoxide. One advantage of forming the insulating layer 26 of siliconnitride is that this material is a good barrier against the diffusion ofmagnetic materials, and it is resistant to a number of etchants that canbe used to selectively etch an overlying oxide layer. The insulatinglayer 26 can be deposited over the magnetic memory cells 24 and polishedback to expose the top surface of the magnetic memory cell 24 using asuitable method, such as, for example, chemical mechanical planarization(CMP). An optional etch stop layer (not shown) can then be depositedover the insulating layer 26 and memory cells 24.

In the illustrated embodiment, an upper electrode is formed on themagnetic memory cell 24 using a damascene process. The process begins bydepositing a temporary layer 36 over the insulating layer 26 and themagnetic memory cell 24, as illustrated in FIG. 1. The temporary layer36 may comprise any material that is selectively removable relative tocopper and the underlying dielectric or optional etch stop, such as, forexample, photoresist, polyimide, bottom antireflective coating (BARC),dielectric antireflective coating (DARC), spin-on glass (SOG),phosphosilicate glass (PSG), boro-phospho-silicate glass (BPSG), or thelike. The material of the temporary layer 36 can preferably withstand apolishing process, such as, for example, CMP.

As illustrated in FIG. 2, the damascene process continues by etching atrench 38 into the temporary layer 36. In the illustrated embodiment,the trench 38 runs into and out of the page, perpendicular to the lowerelectrode 10, and thus traverses several magnetic memory cells 24 in thearray. In some embodiments, the trench 38 has a depth within the rangeof about 50 nm to about 800 nm, preferably about 200 nm. In someembodiments, the width of trench 38 falls within the range of about 50nm to about 300 nm, preferably about 150 nm.

As illustrated in FIG. 3, the damascene process continues by lining thetrench 38 with a barrier layer 42, forming an upper conductive line 44in the lined trench 38, and planarizing the resulting structure. Thesesteps can be performed using a variety of well-known materials andmethods. For example, in some embodiments, the conductive line 44comprises copper, and the barrier layer 42 comprises tantalum, tantalumnitride, or another material that blocks the diffusion of copper. Insome embodiments, the barrier layer 42 has a thickness in the range ofabout 1 nm to about 20 nm, preferably in the range of about 3 nm toabout 10 nm, and more preferably about 5 nm.

In some embodiments, the copper of the conductive line 44 is depositedby chemical or physical vapor deposition. In other embodiments, thecopper is deposited in a two-step process wherein first a seed layer isdeposited by physical vapor deposition and then the trench 38 is filledby electroplating. In some embodiments, the temporary layer 36, barrierlayer 42, and conductive line 44 are planarized by polishing down theexcess copper using, for example, a CMP process. The upper electrode 40comprises the conductive line 44 and the barrier layer 42.

As illustrated in FIG. 4, the damascene process concludes by selectivelyetching the temporary layer 36, thereby exposing the upper electrode 40.Because the upper electrode 40 is formed using a damascene process,rather than a blanket deposition and etching process, the sidewalls ofthe upper electrode 40 are substantially vertical. The temporary layer36 can be selectively etched using any of a variety of well-knownetchants, preferably one that does not attack the upper electrode 40,the magnetic memory cell 24, the insulating layer 26, or the optionaletch stop layer over the insulating layer 26 (if used). For example, insome embodiments, the temporary layer 36 comprises photoresist, and anorganic stripper is used to remove it. In other embodiments, thetemporary layer 36 comprises SOG, and a dilute HF is used to remove it.

As discussed above, it can be desirable to form a magnetic keeper aroundthe upper electrode 40. If the upper electrode 40 were formed using aconventional damascene process, it would remain imbedded in a layer ofmaterial, and it would be somewhat difficult to form a magnetic keeperaround the upper electrode 40. For example, although U.S. Pat. No.6,413,788 (“the '788 patent”) discloses a number of magnetic keeperconfigurations for upper MRAM electrodes formed using conventionaldamascene processes, these configurations can suffer from a number ofdrawbacks, such as, for example, requiring multiple deposition, masking,and etching steps and resulting in magnetic keepers with discontinuousmagnetic layers. By using a damascene process that involves removing thetemporary layer 36, the upper electrode 40 is exposed, the process offorming a magnetic keeper around the upper electrode 40 isadvantageously simplified, and the aspect of avoiding the keepermaterial between the magnetic memory cell 24 and the upper electrode 40is realized.

As illustrated in FIG. 5, a magnetic keeper can be formed around theupper electrode 40. The magnetic keeper may comprise any structure thattends to localize the magnetic field generated by the upper electrode 40when it carries a current. For example, in the illustrated embodiment,the magnetic keeper comprises a magnetic layer 50 and an optionalbarrier layer 52. In a preferred embodiment, the magnetic layer 50comprises a conductive magnetic material, such as, for example,permalloy (Ni—Fe) or Co—Fe. In other embodiments, the magnetic layer 50may comprise a nonconductive magnetic material, such as, for example,ferrites, manganites, cobaltites, and chromites. The barrier layer 52may also comprise a variety of materials, such as, for example, tantalumor tantalum nitride. In a preferred embodiment, the magnetic layer 50 isformed as a continuous layer of magnetic material surrounding the uppersurface and two side surfaces of the upper electrode 40.

In some embodiments, the magnetic layer 50 and the barrier layer 52 eachhave a thickness within the range of about 1 nm to about 20 nm,preferably within the range of about 3 nm to about 10 nm, morepreferably about 5 nm. The magnetic layer 50 and the optional barrierlayer 52 may be formed around the upper electrode 40 using a widevariety of methods that are well-known to those of skill in the art. Forexample, in some embodiments, the layers are deposited as blanket filmsover the upper electrode 40 and then patterned and etched usingconventional techniques. In other embodiments, a conventional platingprocess, such as an electroless plating process or an electroplatingprocess, is used to form the magnetic layer 50 and the barrier layer 52.Such a plating process may present a number of advantages, such aseliminating the need for further patterning and etching steps andforming a magnetic keeper that is self-aligned on the upper electrode40.

Magnetic keepers formed using the process described above exhibit anumber of advantages over other magnetic keepers for upper electrodes ofan MRAM array, such as those disclosed in the '788 patent. For example,unlike the magnetic keepers disclosed in the '788 patent, the magnetickeeper illustrated in FIG. 5 has a continuous magnetic layer 50 incontact with the upper surface and two side surfaces of the upperelectrode 40, as well as a continuous barrier layer 52 in contact withthe magnetic layer. Moreover, the methods of forming magnetic keepersdescribed in the present application require fewer etching steps, whichmay be harmful to the magnetic memory cell 24, than the methods offorming magnetic keepers described in the '788 patent.

As illustrated in FIG. 6, an insulating layer 54 is preferably depositedover the upper electrode 40 that is surrounded by the magnetic keeper.The insulating layer 54 may comprise a variety of nonconductivematerials, such as, for example, various forms of silicon dioxide. Afterthe insulating layer 54 is deposited, it can be planarized using, forexample, a CMP process. The insulating layer 54 advantageously providesstructural support to the structures within the MRAM array and isolatesthe upper electrodes 40 of the array from one another.

There are a number of advantages associated with forming a magnetickeeper around an upper electrode 40 of an MRAM array, as describedabove. For example, the magnetic keeper reduces electromigration byreducing the current required to achieve a given magnetic field at themagnetic memory cell 24 under the upper electrode 40. In addition, bycontaining the magnetic flux of the upper electrode 40 and directing ittoward the magnetic memory cell 24, the magnetic keeper advantageouslyreduces the magnetic field seen by adjacent memory elements.Accordingly, the density of magnetic memory cells 24 within an MRAMarray can advantageously be increased.

Although this invention has been described in terms of certain preferredembodiments, other embodiments that are apparent to those of ordinaryskill in the art, including embodiments that do not provide all of thefeatures and advantages set forth herein, are also within the scope ofthis invention. Accordingly, the scope of the present invention isdefined only by reference to the appended claims.

1. A magnetic memory device in an integrated circuit, comprising: alower electrode formed over a semiconductor substrate; a magnetic memorycell formed over the lower electrode; an upper electrode with a bottomsurface facing toward the magnetic memory cell, a top surface facingaway from the magnetic memory cell and two side surfaces facing awayfrom the magnetic memory cell; and a magnetic keeper comprising at leastone unitary layer of magnetic material completely covering the topsurface and the two side surfaces of the upper electrode.
 2. Themagnetic memory device of claim 1, wherein the magnetic memory cellcomprises a multi-layer tunneling magnetoresistance (TMR) structure. 3.The magnetic memory device of claim 1, wherein the magnetic memory cellcomprises a multi-layer giant magnetoresistance (GMR) structure.
 4. Themagnetic memory device of claim 1, wherein the upper electrode comprisesa conductive line formed in a damascene trench.
 5. The magnetic memorydevice of claim 4, wherein the conductive line comprises copper.
 6. Themagnetic memory device of claim 5, wherein the conductive line hassubstantially vertical sidewalls.
 7. The magnetic memory device of claim5, wherein the width of the conductive line falls within the range ofabout 50 nm to about 300 nm.
 8. The magnetic memory device of claim 4,further comprising a layer of a barrier material disposed at least onthe bottom surface of the upper electrode.
 9. The magnetic memory deviceof claim 8, wherein the layer of the barrier material is furtherdisposed on the side surfaces of the upper electrode.
 10. The magneticmemory device of claim 9, further comprising a second layer of thebarrier material disposed over the unitary layer of magnetic material,where the second layer is unitary.
 11. The magnetic memory device ofclaim 10, wherein the upper electrode comprises copper, and the barriermaterial is tantalum or tantalum nitride.
 12. The magnetic memory deviceof claim 8, wherein the upper electrode comprises copper, and thebarrier material comprises tantalum.
 13. The magnetic memory device ofclaim 8, wherein the upper electrode comprises copper, and the barriermaterial comprises tantalum nitride.
 14. The magnetic memory device ofclaim 1, wherein the magnetic material of the magnetic keeper comprisespermalloy or Co—Fe.
 15. The magnetic memory device of claim 1, whereinthe magnetic keeper further comprises a barrier layer comprising aunitary layer of material over the unitary layer of magnetic material.16. The magnetic memory device of claim 15, wherein the barrier layercomprises tantalum.
 17. The magnetic memory device of claim 15, whereinthe barrier layer comprises tantalum nitride.
 18. The magnetic memorydevice of claim 1, wherein a top surface of the magnetic memory cell isin electrical contact with the upper electrode.
 19. The magnetic memorydevice of claim 1, wherein the top surface of the upper electrode isflat.
 20. The magnetic memory device of claim 1, wherein the unitarylayer of magnetic material for the magnetic keeper has a cross-sectionalprofile without discontinuities.
 21. The magnetic memory device of claim1, wherein the unitary layer of magnetic material for the magnetickeeper has a convex shape at corners defined by the top surface and sidesurfaces of the upper electrode when viewed from a side of the magnetickeeper opposite the upper electrode.
 22. An integrated circuit elementcomprising: a copper structure having a top surface and at least twoside surfaces; and a multi-layer coating comprising at least a firstcontinuous layer of a first material and a second continuous layer of asecond material different from the first material, the multi-layercoating adjacent to the top surface and extending completely down atleast two side surfaces of the copper structure.
 23. The magnetic memorydevice of claim 22, wherein the multi-layer coating has across-sectional profile without discontinuities.
 24. The magnetic memorydevice of claim 22, wherein the multi-layer coating has a convex shapeat corners defined by the top surface and side surfaces of the upperelectrode when viewed from a side of the magnetic keeper opposite theupper electrode.
 25. The magnetic memory device of claim 22, wherein thefirst continuous layer of the first material comprises a barrier layerand the second continuous layer of the second material comprises amagnetic material.
 26. The magnetic memory device of claim 22, whereinthe copper structure comprises a conductive line of copper having abarrier layer disposed along a bottom surface and the two side surfaces.27. A magnetic memory device in an integrated circuit, comprising: alower electrode formed over a semiconductor substrate; a magnetic memorycell formed over the lower electrode; an upper electrode of copper witha bottom surface facing toward the magnetic memory cell, a top surfacefacing away from the magnetic memory cell and two side surfaces facingaway from the magnetic memory cell; and a magnetic keeper comprising atleast one layer of magnetic material completely covering the top surfaceand the two side surfaces of the upper electrode, wherein the layer ofmagnetic material for the magnetic keeper has a convex shape at cornersdefined by the top surface and side surfaces of the upper electrode whenviewed from a side of the magnetic keeper opposite the upper electrode.28. The magnetic memory device of claim 27, wherein the top surface ofthe upper electrode is flat.
 29. The magnetic memory device of claim 27,further comprising a barrier layer of tantalum or tantalum nitridedisposed between the bottom surface of the upper electrode and themagnetic memory cell.
 30. The magnetic memory device of claim 29,wherein the barrier layer is further disposed between the side surfacesof the upper electrode and the magnetic keeper.
 31. The magnetic memorydevice of claim 31, further comprising a second barrier layer disposedoutside the magnetic keeper.
 32. The magnetic memory device of claim 27,further comprising a barrier layer disposed outside the magnetic keeper.